[PATCH 0/2] riscv: mm: Some optimizations for tlb flush

[Xu Lu]

Some optimizations for tlb flush on RISC-V smp:

1. Apply Svinval in update_mmu_cache().
2. Clear bit of current cpu in mm_cpumask after
local_flush_tlb_all_asid().

Xu Lu (2):
  riscv: mm: Apply svinval in update_mmu_cache()
  riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid

 arch/riscv/include/asm/pgtable.h  | 16 +++++++-
 arch/riscv/include/asm/tlbflush.h | 23 +++++++++++
 arch/riscv/mm/tlbflush.c          | 64 ++++++++++++-------------------
 3 files changed, 63 insertions(+), 40 deletions(-)

-- 
2.20.1