[PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller

[Hal Feng]

> On 23.08.25 18:02, E Shattow wrote:
>
> Add JH7110 SoC DDR external memory controller.
> 
> Signed-off-by: E Shattow <e at freeshell.de>

Reviewed-by: Hal Feng <hal.feng at starfivetech.com>

Best regards,
Hal

> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 0ba74ef04679..f3876660c07f 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -931,6 +931,18 @@ watchdog at 13070000 {
>  				 <&syscrg JH7110_SYSRST_WDT_CORE>;
>  		};
> 
> +		memory-controller at 15700000 {
> +			compatible = "starfive,jh7110-dmc";
> +			reg = <0x0 0x15700000 0x0 0x10000>,
> +			      <0x0 0x13000000 0x0 0x10000>;
> +			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> +			clock-names = "pll";
> +			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> +				 <&syscrg JH7110_SYSRST_DDR_OSC>,
> +				 <&syscrg JH7110_SYSRST_DDR_APB>;
> +			reset-names = "axi", "osc", "apb";
> +		};
> +
>  		crypto: crypto at 16000000 {
>  			compatible = "starfive,jh7110-crypto";
>  			reg = <0x0 0x16000000 0x0 0x4000>;
> --
> 2.50.0