[PATCH 05/18] riscv: asm: use .insn for making custom instructioons

[Ben Dooks]

Using .word breaks with big endian builds, making something which
is not a valid or worse an instruction or pair that does something
which is not intended.

Signed-off-by: Ben Dooks <ben.dooks at codethink.co.uk>
---
 arch/riscv/include/asm/insn-def.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
index d5adbaec1d01..2a3019bc1a3b 100644
--- a/arch/riscv/include/asm/insn-def.h
+++ b/arch/riscv/include/asm/insn-def.h
@@ -256,10 +256,17 @@
 	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(3),		\
 	       SIMM12((offset) & 0xfe0), RS1(base))
 
+#ifndef CONFIG_AS_HAS_INSN
 #define RISCV_PAUSE	".4byte 0x100000f"
 #define ZAWRS_WRS_NTO	".4byte 0x00d00073"
 #define ZAWRS_WRS_STO	".4byte 0x01d00073"
 #define RISCV_NOP4	".4byte 0x00000013"
+#else
+#define RISCV_PAUSE	".insn 0x100000f"
+#define ZAWRS_WRS_NTO	".insn 0x00d00073"
+#define ZAWRS_WRS_STO	".insn 0x01d00073"
+#define RISCV_NOP4	".insn 0x00000013"
+#endif
 
 #define RISCV_INSN_NOP4	_AC(0x00000013, U)
 
-- 
2.37.2.352.g3c44437643