[PATCH v5 0/7] riscv: Add support for xmipsexectl

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti at rivosinc.com>:

On Thu, 24 Jul 2025 17:23:24 +0200 you wrote:
> This patch series adds support for the xmipsexectl vendor extension.
> A new hardware probe key has also been added to allow userspace to probe for MIPS vendor extensions.
> 
> Additionally, since the standard Zihintpause PAUSE instruction encoding is not supported on some MIPS CPUs,
> an errata was implemented for replacing this instruction with the xmipsexectl MIPS.PAUSE alternative encoding.
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic at htecgroup.com>
> 
> [...]

Here is the summary with links:
  - [v5,1/7] dt-bindings: riscv: Add xmipsexectl ISA extension description
    https://git.kernel.org/riscv/c/06d48c2c4f83
  - [v5,2/7] riscv: Add xmipsexectl as a vendor extension
    https://git.kernel.org/riscv/c/02b01dfaf4fa
  - [v5,3/7] riscv: Add xmipsexectl instructions
    https://git.kernel.org/riscv/c/d85071f97570
  - [v5,4/7] riscv: hwprobe: Add MIPS vendor extension probing
    https://git.kernel.org/riscv/c/20b80c735c05
  - [v5,5/7] riscv: hwprobe: Document MIPS xmipsexectl vendor extension
    https://git.kernel.org/riscv/c/c714fbc023df
  - [v5,6/7] riscv: Add tools support for xmipsexectl
    https://git.kernel.org/riscv/c/378afb53aab2
  - [v5,7/7] riscv: errata: Fix the PAUSE Opcode for MIPS P8700
    https://git.kernel.org/riscv/c/838218910ea3

You are awesome, thank you!
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