[RESEND v4 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema

[Rob Herring (Arm)]

On Sat, 15 Jun 2024 07:45:03 +0530, Kanak Shilledar wrote:
> Convert the RISC-V Hart-Level Interrupt Controller (HLIC) to newer
> DT schema, Created DT schema based on the .txt file which had
> `compatible`, `#interrupt-cells` and `interrupt-controller` as
> required properties.
> Changes made with respect to original file:
> - Changed the example to just use interrupt-controller instead of
> using the whole cpu block
> - Changed the example compatible string.
> 
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
> Signed-off-by: Kanak Shilledar <kanakshilledar at gmail.com>
> ---
> Changes in v4:
> - Change DCO email to @gmail.com
> Changes in v3:
> - Remove reference to `interrupt-controller` in `riscv/cpus.yaml`.
> Changes in v2:
> - Update the maintainers list.
> - Add reference to `interrupt-controller` in `riscv/cpus.yaml`.
> - Update compatible property with the reference in `cpus.yaml`.
> - Include description for '#interrupt-cells' property.
> - Change '#interrupt-cells' property to have `const: 1` as per the
> text binding.
> - Fixed the warning thrown by `/renesas/r9a07g043f01-smarc.dtb`.
> ---
>  .../interrupt-controller/riscv,cpu-intc.txt   | 52 -------------
>  .../interrupt-controller/riscv,cpu-intc.yaml  | 73 +++++++++++++++++++
>  2 files changed, 73 insertions(+), 52 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
> 

Applied, thanks!