[RFC PATCH v2 01/10] iommu/riscv: add RISC-V IOMMU PMU support
Zong Li
zong.li at sifive.com
Mon Jun 17 18:14:49 PDT 2024
On Mon, Jun 17, 2024 at 10:55 PM Jason Gunthorpe <jgg at ziepe.ca> wrote:
>
> On Fri, Jun 14, 2024 at 10:21:47PM +0800, Zong Li wrote:
> > This patch implements the RISC-V IOMMU hardware performance monitor, it
> > includes the counting ans sampling mode.
> >
> > Specification doesn't define the event ID for counting the number of
> > clock cycles, there is no associated iohpmevt0. But we need an event for
> > counting cycle in perf, reserve the maximum number of event ID for it now.
>
> Why is this part of the nesting series?
As you mentioned, it should be a separate patch set, let me submit it
individually in the next version. Thanks
>
> Jason
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