[PATCH v2 1/6] RISC-V: Add Zicclsm to cpufeature and hwprobe

[Andy Chiu]

On Fri, Jun 14, 2024 at 4:09 PM Conor Dooley <conor.dooley at microchip.com> wrote:
>
> On Thu, Jun 13, 2024 at 03:16:10PM -0400, Jesse Taube wrote:
> > > Zicclsm Misaligned loads and stores to main memory regions with both
> > > the cacheability and coherence PMAs must be supported.
> > > Note:
> > > This introduces a new extension name for this feature.
> > > This requires misaligned support for all regular load and store
> > > instructions (including scalar and vector) but not AMOs or other
> > > specialized forms of memory access. Even though mandated, misaligned
> > > loads and stores might execute extremely slowly. Standard software
> > > distributions should assume their existence only for correctness,
> > > not for performance.
> >
> > Detecing zicclsm allows the kernel to report if the
> > hardware supports misaligned accesses even if support wasn't probed.
> >
> > This is useful for usermode to know if vector misaligned accesses are
> > supported.
> >
> > Signed-off-by: Jesse Taube <jesse at rivosinc.com>
>
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

Reviewed-by: Andy Chiu <andy.chiu at sifive.com>