[PATCH v3 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent
daire.mcnamara at microchip.com
daire.mcnamara at microchip.com
Wed Jun 12 04:22:13 PDT 2024
From: Conor Dooley <conor.dooley at microchip.com>
PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara at microchip.com>
---
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index f7a3c2636355..c84e1ae20532 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -52,6 +52,8 @@ properties:
items:
pattern: '^fic[0-3]$'
+ dma-noncoherent: true
+
interrupts:
minItems: 1
items:
--
2.34.1
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