[RFC PATCH v0] RISCV: Report vector unaligned accesses hwprobe

[Conor Dooley]

On Tue, Jun 04, 2024 at 12:42:10PM -0400, Jesse Taube wrote:
> On 6/4/24 12:24, Jesse Taube wrote:
> > diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
> > index a9a6bcb02acf..92a84239beaa 100644
> > --- a/arch/riscv/kernel/unaligned_access_speed.c
> > +++ b/arch/riscv/kernel/unaligned_access_speed.c
> > @@ -20,6 +20,7 @@
> >   #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
> >   DEFINE_PER_CPU(long, misaligned_access_speed);
> > +DEFINE_PER_CPU(long, vector_misaligned_access) = RISCV_HWPROBE_VEC_MISALIGNED_UNKNOWN;
> >   #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
> >   static cpumask_t fast_misaligned_access;
> > @@ -264,6 +265,8 @@ static int check_unaligned_access_all_cpus(void)
> >   {
> >   	bool all_cpus_emulated = check_unaligned_access_emulated_all_cpus();
> 
> There was talks about Zicclsm, but spike doesnt have support for Zicclsm
> afaik,

Support for Zicclsm just means that it can perform misaligned loads and
stores to cache coherent memory. I guess support in Spike would involve
setting that in its devicetree iff/when that's the case.

> but I was wondering if i should add Zicclsm to cpufeature and aswell.

Ye, please do add detection for Zicclsm. I think that should be fairly
straightforward to do, nothing too special to document.

Cheers,
Conor.
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