[PATCH v2 7/9] irqchip: Add RISC-V advanced PLIC driver

[Anup Patel]

On Fri, Nov 24, 2023 at 8:33 AM 谢 波 <xiebo_60 at live.com> wrote:
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> Hello all,
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> I have a question regarding the handling of potential issues during the MSI interrupt sending process. It appears that if the APLIC target register's value is modified during the MSI interrupt sending process, it could potentially lead to MSI interrupt send failures. The code doesn't seem to account for this scenario or take appropriate measures.
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> I am reaching out to seek clarification on whether this situation has been considered and if there are specific reasons for not addressing it in the code. Your insights into this matter would be highly appreciated.
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> Thank you for your time, and I look forward to your response.

This has been taken care of in the IMSIC driver in the irq_set_affinity()
because the IMSIC driver manages the re-writing of MSI messages
upon IRQ affinity changes.

Please look at PATCH7 and PATCH8 of the "[PATCH v11 00/14] Linux
RISC-V AIA Support" series.
(Refer, https://www.spinics.net/lists/devicetree/msg643764.html)

Regards,
Anup

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> Best regards
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>