[PATCH v3 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
Conor Dooley
conor at kernel.org
Fri Nov 17 06:30:00 PST 2023
On Fri, Nov 17, 2023 at 08:30:21PM +0800, Inochi Amaoto wrote:
> >
> >On 17/11/2023 06:07, Inochi Amaoto wrote:
> >> The timer registers of aclint don't follow the clint layout and can
> >> be mapped on any different offset. As sg2042 uses separated timer
> >> and mswi for its clint, it should follow the aclint spec and have
> >> separated registers.
> >>
> >> The previous patch introduced a new type of T-HEAD aclint timer which
> >> has clint timer layout. Although it has the clint timer layout, it
> >> should follow the aclint spec and uses the separated mtime and mtimecmp
> >> regs. So a ABI change is needed to make the timer fit the aclint spec.
> >>
> >> To make T-HEAD aclint timer more closer to the aclint spec, use
> >> regs-names to represent the mtimecmp register, which can avoid hack
> >> for unsupport mtime register of T-HEAD aclint timer.
> >>
> >
> >I don't understand this reasoning. You had one entry, you still have one
> >entry. Adding reg-names (not regs-names) does not change it.
> >
>
> If no "reg-names", all the register of ACLINT should be defined. However,
> T-HEAD aclint timer of sg2042 only supports mtimecmp register. If no extra
> prompt is provided for the SBI, it will fail to recognize aclint timer
> registers when parsing the aclint node with one reg entry.
>
> There is another way to avoid this by using an empty entry to identify
> unsupported mtime, but Conor have already rejected this. See [1].
>
> Link: https://lore.kernel.org/all/20231114-skedaddle-precinct-66c8897227bb@squawk/ [1]
Perhaps you misunderstood my suggestion. I was looking for _both_
registers to be defined in the binding as well as adding reg-names as a
required property. Doing what you have here might work for your use
case, but does not make sense from a bindings point of view as there is
no way to describe the mtime register, should it exist in another SoC.
Cheers,
Conor
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