[PATCH v2 2/2] riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format
Chen Wang
unicorn_wang at outlook.com
Mon Nov 13 17:06:52 PST 2023
On 2023/11/14 8:45, Inochi Amaoto wrote:
> Change the timer layout in the dtb to fit the format that needed by
> the SBI.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
> ---
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++++++-----------
> 1 file changed, 48 insertions(+), 32 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 93256540d078..0b5d93b5c783 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -93,144 +93,160 @@ clint_mswi: interrupt-controller at 7094000000 {
> <&cpu63_intc 3>;
> };
>
> - clint_mtimer0: timer at 70ac000000 {
> + clint_mtimer0: timer at 70ac004000 {
The address of timer register is changed, and I guess it is another
change not directly related to the topic of this patch.
Can you please add some comments in the commit message?
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac004000 0x00000000 0x00000000>,
Why the length of first item is zero? Can you please add some
clarification in commit message?
> + <0x00000070 0xac004000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu0_intc 7>,
> <&cpu1_intc 7>,
> <&cpu2_intc 7>,
> <&cpu3_intc 7>;
> };
>
> - clint_mtimer1: timer at 70ac010000 {
> + clint_mtimer1: timer at 70ac014000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac014000 0x00000000 0x00000000>,
> + <0x00000070 0xac014000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu4_intc 7>,
> <&cpu5_intc 7>,
> <&cpu6_intc 7>,
> <&cpu7_intc 7>;
> };
>
> - clint_mtimer2: timer at 70ac020000 {
> + clint_mtimer2: timer at 70ac024000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac024000 0x00000000 0x00000000>,
> + <0x00000070 0xac024000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu8_intc 7>,
> <&cpu9_intc 7>,
> <&cpu10_intc 7>,
> <&cpu11_intc 7>;
> };
>
> - clint_mtimer3: timer at 70ac030000 {
> + clint_mtimer3: timer at 70ac034000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac034000 0x00000000 0x00000000>,
> + <0x00000070 0xac034000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu12_intc 7>,
> <&cpu13_intc 7>,
> <&cpu14_intc 7>,
> <&cpu15_intc 7>;
> };
>
> - clint_mtimer4: timer at 70ac040000 {
> + clint_mtimer4: timer at 70ac044000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac044000 0x00000000 0x00000000>,
> + <0x00000070 0xac044000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu16_intc 7>,
> <&cpu17_intc 7>,
> <&cpu18_intc 7>,
> <&cpu19_intc 7>;
> };
>
> - clint_mtimer5: timer at 70ac050000 {
> + clint_mtimer5: timer at 70ac054000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac054000 0x00000000 0x00000000>,
> + <0x00000070 0xac054000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu20_intc 7>,
> <&cpu21_intc 7>,
> <&cpu22_intc 7>,
> <&cpu23_intc 7>;
> };
>
> - clint_mtimer6: timer at 70ac060000 {
> + clint_mtimer6: timer at 70ac064000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac064000 0x00000000 0x00000000>,
> + <0x00000070 0xac064000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu24_intc 7>,
> <&cpu25_intc 7>,
> <&cpu26_intc 7>,
> <&cpu27_intc 7>;
> };
>
> - clint_mtimer7: timer at 70ac070000 {
> + clint_mtimer7: timer at 70ac074000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac074000 0x00000000 0x00000000>,
> + <0x00000070 0xac074000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu28_intc 7>,
> <&cpu29_intc 7>,
> <&cpu30_intc 7>,
> <&cpu31_intc 7>;
> };
>
> - clint_mtimer8: timer at 70ac080000 {
> + clint_mtimer8: timer at 70ac084000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac084000 0x00000000 0x00000000>,
> + <0x00000070 0xac084000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu32_intc 7>,
> <&cpu33_intc 7>,
> <&cpu34_intc 7>,
> <&cpu35_intc 7>;
> };
>
> - clint_mtimer9: timer at 70ac090000 {
> + clint_mtimer9: timer at 70ac094000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac094000 0x00000000 0x00000000>,
> + <0x00000070 0xac094000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu36_intc 7>,
> <&cpu37_intc 7>,
> <&cpu38_intc 7>,
> <&cpu39_intc 7>;
> };
>
> - clint_mtimer10: timer at 70ac0a0000 {
> + clint_mtimer10: timer at 70ac0a4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0a4000 0x00000000 0x00000000>,
> + <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu40_intc 7>,
> <&cpu41_intc 7>,
> <&cpu42_intc 7>,
> <&cpu43_intc 7>;
> };
>
> - clint_mtimer11: timer at 70ac0b0000 {
> + clint_mtimer11: timer at 70ac0b4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0b4000 0x00000000 0x00000000>,
> + <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu44_intc 7>,
> <&cpu45_intc 7>,
> <&cpu46_intc 7>,
> <&cpu47_intc 7>;
> };
>
> - clint_mtimer12: timer at 70ac0c0000 {
> + clint_mtimer12: timer at 70ac0c4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0c4000 0x00000000 0x00000000>,
> + <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu48_intc 7>,
> <&cpu49_intc 7>,
> <&cpu50_intc 7>,
> <&cpu51_intc 7>;
> };
>
> - clint_mtimer13: timer at 70ac0d0000 {
> + clint_mtimer13: timer at 70ac0d4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0d4000 0x00000000 0x00000000>,
> + <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu52_intc 7>,
> <&cpu53_intc 7>,
> <&cpu54_intc 7>,
> <&cpu55_intc 7>;
> };
>
> - clint_mtimer14: timer at 70ac0e0000 {
> + clint_mtimer14: timer at 70ac0e4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0e4000 0x00000000 0x00000000>,
> + <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu56_intc 7>,
> <&cpu57_intc 7>,
> <&cpu58_intc 7>,
> <&cpu59_intc 7>;
> };
>
> - clint_mtimer15: timer at 70ac0f0000 {
> + clint_mtimer15: timer at 70ac0f4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0f4000 0x00000000 0x00000000>,
> + <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
> interrupts-extended = <&cpu60_intc 7>,
> <&cpu61_intc 7>,
> <&cpu62_intc 7>,
> --
> 2.42.1
>
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