[PATCH v2 00/11] riscv: ASID-related and UP-related TLB flush enhancements

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer at rivosinc.com>:

On Sat, 28 Oct 2023 16:11:58 -0700 you wrote:
> While reviewing Alexandre Ghiti's "riscv: tlb flush improvements"
> series[1], I noticed that most TLB flush functions end up as a call to
> local_flush_tlb_all() when SMP is disabled. This series resolves that.
> Along the way, I realized that we should be using single-ASID flushes
> wherever possible, so I implemented that as well.
> 
> [1]: https://lore.kernel.org/linux-riscv/20231019140151.21629-1-alexghiti@rivosinc.com/
> 
> [...]

Here is the summary with links:
  - [v2,01/11] riscv: Improve tlb_flush()
    https://git.kernel.org/riscv/c/c5e9b2c2ae82
  - [v2,02/11] riscv: Improve flush_tlb_range() for hugetlb pages
    https://git.kernel.org/riscv/c/c962a6e74639
  - [v2,03/11] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
    https://git.kernel.org/riscv/c/9d4e8d5fa7db
  - [v2,04/11] riscv: Improve flush_tlb_kernel_range()
    https://git.kernel.org/riscv/c/5e22bfd520ea
  - [v2,05/11] riscv: mm: Combine the SMP and UP TLB flush code
    (no matching commit)
  - [v2,06/11] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
    (no matching commit)
  - [v2,07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros
    (no matching commit)
  - [v2,08/11] riscv: mm: Use a fixed layout for the MM context ID
    (no matching commit)
  - [v2,09/11] riscv: mm: Make asid_bits a local variable
    (no matching commit)
  - [v2,10/11] riscv: mm: Preserve global TLB entries when switching contexts
    (no matching commit)
  - [v2,11/11] riscv: mm: Always use ASID to flush MM contexts
    (no matching commit)

You are awesome, thank you!
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