[PATCH v2 0/8] ISA string parser cleanups++

[Conor Dooley]

From: Conor Dooley <conor.dooley at microchip.com>

This stuff goes on top of riscv/for-next plus this series from Yangyu
that made me go looking at the ISA string parser again:
https://lore.kernel.org/all/tencent_E6911C8D71F5624E432A1AFDF86804C3B509@qq.com/

With that out of the way, here are some cleanups for our riscv,isa
handling.
One of these patches is yoinked from Sunil's ACPI series & tweaked
slightly since this needs to apply independently of that, that runs the
isa string parsing loop only over _possible_ cpus.

Other than that, there are some bits that were discussed with Drew on
the "should we allow caps" threads that I have now created patches for:
- splitting of riscv_of_processor_hartid() into two distinct functions,
  one for use purely during early boot, prior to the establishment of
  the possible-cpus mask & another to fit the other current use-cases.
- this allows us to then completely skip some validation of the hartid
  in the parser.
- the biggest diff in the series is a rework of the comments in the
  parser, as I have mostly found the existing (sparse) ones to not be
  all that helpful whenever I have to go back and look at it.
- from writing the comments, I found a conditional doing a bit of a
  dance that I found counter-intuitive, so I've had a go at making that
  match what I would expect a little better.
- `i` implies 4 other extensions, so add them as extensions and set
  them for the craic. Sure why not like.

Clearly this material will conflict with the addition of ACPI support,
which I figure is likely to land first. I expect to rebase if it does.
There's a far more trivial numbering conflict with Evan's Zb* additions.

Cheers,
Conor.

Changes in v2:
- Pick up tags on most patches
- Drop some dt specifics from a parser comment
- Add Zicntr and Zihpm to the "always report" patch
- Note the Zicntr and Zihpm bits in the binding in a new patch

CC: Paul Walmsley <paul.walmsley at sifive.com>
CC: Palmer Dabbelt <palmer at dabbelt.com>
CC: Conor Dooley <conor.dooley at microchip.com>
CC: Andrew Jones <ajones at ventanamicro.com>
CC: Sunil V L <sunilvl at ventanamicro.com>
CC: Yangyu Chen <cyy at cyyself.name>
CC: Rob Herring <robh+dt at kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
CC: devicetree at vger.kernel.org
CC: linux-riscv at lists.infradead.org

Conor Dooley (7):
  RISC-V: simplify register width check in ISA string parsing
  RISC-V: split early & late of_node to hartid mapping
  RISC-V: validate riscv,isa at boot, not during ISA string parsing
  RISC-V: rework comments in ISA string parser
  RISC-V: remove decrement/increment dance in ISA string parser
  dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm
    support
  RISC-V: always report presence of extenstions formerly part of the
    base ISA

Sunil V L (1):
  RISC-V: only iterate over possible CPUs in ISA string parser

 .../devicetree/bindings/riscv/cpus.yaml       |   4 +-
 arch/riscv/include/asm/hwcap.h                |   4 +
 arch/riscv/include/asm/processor.h            |   1 +
 arch/riscv/kernel/cpu.c                       |  34 ++++-
 arch/riscv/kernel/cpufeature.c                | 116 +++++++++++++-----
 arch/riscv/kernel/smpboot.c                   |   2 +-
 6 files changed, 126 insertions(+), 35 deletions(-)


base-commit: c2d3c8441e3ddbfe41fea9282ddc6ee372e154cd
prerequisite-patch-id: 50cc6c119a7f8f60b06829b2fafc90c9817f532c
prerequisite-patch-id: 4e2f66d8590db938d2e1a4e9bfaad58ee0ab3525

Dependencies:
https://lore.kernel.org/all/tencent_E6911C8D71F5624E432A1AFDF86804C3B509@qq.com/
-- 
2.39.2