[PATCH -next v20 07/26] riscv: Introduce Vector enable/disable helpers

[Andy Chiu]

From: Greentime Hu <greentime.hu at sifive.com>

These are small and likely to be frequently called so implement as
inline routines (vs. function call).

Co-developed-by: Guo Ren <guoren at linux.alibaba.com>
Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen at sifive.com>
Signed-off-by: Vincent Chen <vincent.chen at sifive.com>
Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
Signed-off-by: Vineet Gupta <vineetg at rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu at sifive.com>
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner at vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner at vrull.eu>
Reviewed-by: Palmer Dabbelt <palmer at rivosinc.com>
---
 arch/riscv/include/asm/vector.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index bdbb05b70151..51bb37232943 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -11,12 +11,23 @@
 #ifdef CONFIG_RISCV_ISA_V
 
 #include <asm/hwcap.h>
+#include <asm/csr.h>
 
 static __always_inline bool has_vector(void)
 {
 	return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);
 }
 
+static __always_inline void riscv_v_enable(void)
+{
+	csr_set(CSR_SSTATUS, SR_VS);
+}
+
+static __always_inline void riscv_v_disable(void)
+{
+	csr_clear(CSR_SSTATUS, SR_VS);
+}
+
 #else /* ! CONFIG_RISCV_ISA_V  */
 
 static __always_inline bool has_vector(void) { return false; }
-- 
2.17.1