[PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support

[Jisheng Zhang]

On Thu, Jul 27, 2023 at 08:54:59AM +0800, Xi Ruoyao wrote:
> On Thu, 2023-07-27 at 08:14 +0800, Xi Ruoyao wrote:
> > On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote:
> > > which dts r u using? see below.
> > > 
> > > > 
> > > > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no patches) can
> > > > miscompile the kernel?
> > 
> > /* snip */
> > 
> > > > Boot HART ID              : 0
> > > > Boot HART Domain          : root
> > > > Boot HART Priv Version    : v1.11
> > > > Boot HART Base ISA        : rv64imafdcvx
> > > 
> > > what? I don't think the mainline dts provide v and x. 
> > 
> > I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb
> > into /boot and loaded it with u-boot "load" command onto 0x46000000, and
> > passed this address to the booti command.
> > 
> > But maybe I've copied the wrong file or made some other mistake... I'll
> > recheck.
> 
> Hmm, and if I read OpenSBI code correctly, this line reflects the
> content of the misa CSR, not the DT riscv,isa value.
> 

Aha indeed the "vx" isa extensions are not from the DT riscv,isa
property. I will try your opensbi/linux/uboot combinations on my
lpi4a board tomorrow.

> The log of successful boot provided by Drew also contains
> "rv64imafdcvx":
> 
> https://gist.github.com/pdp7/23259595a7570f1f11086d286e16dfb6
>