[PATCH RFC 4/4] mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520

[Jisheng Zhang]

On Mon, Jul 24, 2023 at 05:59:18PM -0700, Drew Fustini wrote:
> Add basic support for the T-Head TH1520 SoC mmc controller. The new
> compatible "thead,th1520-dwcmshc" enables basic support by:

Hi Drew,

> 
>  - Enabling v4 mode to properly communicate with the mmc device
>  - Setting quirk to disable ADMA
>  - Setting flag to disable SDMA and force PIO mode
>  - Turing .reset op into a no-op as the driver does not yet know how to
>    configure the phy. Rely on the vendor u-boot to have configured the
>    phy and do not reset the controller in Linux.

The last three itmes are not acceptable. The controller supports ADMA
well, can you plz bring in the phy driver? We can't rely on bootloader to
configure phy.

> 
> Signed-off-by: Drew Fustini <dfustini at baylibre.com>
> ---
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 42 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index e68cd87998c8..8573aff25a81 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -337,6 +337,14 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
>  	sdhci_reset(host, mask);
>  }
>  
> +static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
> +{
> +	/*
> +	 * MMC controller and phy is configured by vendor u-boot so
> +	 * take the simplistic approach of not doing reset in Linux.
> +	 */
> +}
> +
>  static const struct sdhci_ops sdhci_dwcmshc_ops = {
>  	.set_clock		= sdhci_set_clock,
>  	.set_bus_width		= sdhci_set_bus_width,
> @@ -355,6 +363,15 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
>  	.adma_write_desc	= dwcmshc_adma_write_desc,
>  };
>  
> +static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
> +	.set_clock		= sdhci_set_clock,
> +	.set_bus_width		= sdhci_set_bus_width,
> +	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
> +	.get_max_clock		= dwcmshc_get_max_clock,
> +	.reset			= th1520_sdhci_reset,
> +	.adma_write_desc	= dwcmshc_adma_write_desc,
> +};
> +
>  static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
>  	.ops = &sdhci_dwcmshc_ops,
>  	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> @@ -378,6 +395,13 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
>  		   SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
>  };
>  
> +static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {
> +	.ops = &sdhci_dwcmshc_th1520_ops,
> +	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_BROKEN_DMA |
> +		  SDHCI_QUIRK_BROKEN_ADMA,
> +	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> +};
> +
>  static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
>  {
>  	int err;
> @@ -434,6 +458,10 @@ static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv
>  }
>  
>  static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
> +	{
> +		.compatible = "thead,th1520-dwcmshc",
> +		.data = &sdhci_dwcmshc_th1520_pdata,
> +	},
>  	{
>  		.compatible = "rockchip,rk3588-dwcmshc",
>  		.data = &sdhci_dwcmshc_rk35xx_pdata,
> @@ -546,6 +574,20 @@ static int dwcmshc_probe(struct platform_device *pdev)
>  		sdhci_enable_v4_mode(host);
>  #endif
>  
> +	if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) {
> +		/*
> +		 * The controller needs v4 mode enabled to properly
> +		 * communicate with the mmc device.
> +		 */
> +		sdhci_enable_v4_mode(host);
> +
> +		/*
> +		 * Set flag so the SDHCI host core will disable DMA
> +		 * and use PIO mode.
> +		 */
> +		host->flags &= ~SDHCI_USE_SDMA;
> +	}
> +
>  	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
>  
>  	err = sdhci_setup_host(host);
> 
> -- 
> 2.34.1
>