[PATCH v2 1/6] RISC-V: Detect Smstateen extension

[Conor Dooley]

Hey,

On Fri, Jul 21, 2023 at 10:49:54AM +0200, Andrew Jones wrote:
> On Fri, Jul 21, 2023 at 01:24:34PM +0530, Mayuresh Chitale wrote:
> > Extend the ISA string parsing to detect the Smstateen extension
> > 
> > Signed-off-by: Mayuresh Chitale <mchitale at ventanamicro.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> >  arch/riscv/include/asm/hwcap.h                          | 1 +
> >  arch/riscv/kernel/cpu.c                                 | 1 +
> >  arch/riscv/kernel/cpufeature.c                          | 1 +
> >  4 files changed, 9 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index cc1f546fdbdc..1e6d0e182be1 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -128,6 +128,12 @@ properties:
> >              changes to interrupts as frozen at commit ccbddab ("Merge pull
> >              request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
> >  
> > +        - const: smstateen
> > +          description: |
> > +            The standard Smstateen extension for controlling accesss to CSRs
>                                                                 ^ access
> 
> > +            added by other Risc-V extensions in H/S/VS/U/VU modes and as

s/Risc-V/RISC-V/. Let's not invent new stylisations please.

> s/and//
> 
> > +            ratified at commit a28bfae (Ratified (#7)).

An "of riscv-state-enable" at the end might be helpful too.

Either way, neither checkpatch nor get_maintainer were run on this v2
patch, the former would have pointed out that dt-binding changes should
be made in their own patches.

The C stuff is fine, but this needs to be split in two.

Thanks,
Conor.
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