[PATCH v8 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110

[Conor Dooley]

On Thu, Jul 13, 2023 at 07:38:53PM +0800, Xingyu Wu wrote:
> This patch serises are base on the basic JH7110 SYSCRG/AONCRG
> drivers and add new partial clock drivers and reset supports
> about System-Top-Group(STG), Image-Signal-Process(ISP)
> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These
> clocks and resets could be used by DMA, VIN and Display modules.
> 
> Patches 1 and 2 are about the System-Top-Group clock and reset
> generator(STGCRG) part. The first patch adds docunmentation to
> describe STG bindings, and the second patch adds clock driver to
> support STG clocks and resets as auxiliary device for JH7110.
> 
> Patches 3 and 4 are about the Image-Signal-Process clock and reset
> gennerator(ISPCRG) part. The first patch adds docunmentation to
> describe ISP bindings, and the second patch adds clock driver to
> support ISP clocks and resets as auxiliary device for JH7110.
> And ISP clocks should power on and enable the SYSCRG clocks first
> before registering.
> 
> Patches 5 and 6 are about the Video-Output clock and reset
> generator(VOUTCRG) part. The first patch adds docunmentation to
> describe VOUT bindings, and the second patch adds clock driver to
> support VOUT clocks and resets as auxiliary device for JH7110.
> And VOUT clocks also should power on and enable the SYSCRG clocks
> first before registering.
> 
> Patch 7 adds struct members to support STG/ISP/VOUT resets.

> Patch 8 adds external clocks which ISP and VOUT clock driver need.
> Patch 9 adds device node about STGCRG, ISPCRG and VOUTCRG to JH7110 dts.

b4 did not detect this correctly, but I picked these 2 up too.
They should be in next tomorrow.

Please let your co-workers know that they should resend anything that I
didn't sent a thanks email for today, as it failed to apply (eg DMA,
eMMC).

Thanks,
Conor.

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