(subset) [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC

[Conor Dooley]

From: Conor Dooley <conor.dooley at microchip.com>

On Mon, 17 Jul 2023 10:30:33 +0800, Xingyu Wu wrote:
> This patch serises are to add PLL clocks driver and providers by writing
> and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add
> documentation and nodes to describe StarFive System Controller(syscon)
> Registers. This patch serises are based on Linux 6.4.
> 
> PLLs are high speed, low jitter frequency synthesizers in JH7110.
> Each PLL clock works in integer mode or fraction mode by some dividers,
> and the dividers are set in several syscon registers.
> The formula for calculating frequency is:
> Fvco = Fref * (NI + NF) / M / Q1
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[6/7] riscv: dts: starfive: jh7110: Add syscon nodes
      https://git.kernel.org/conor/c/3fcbcfc496f0
[7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
      https://git.kernel.org/conor/c/3e6670a28b00

Thanks,
Conor.