[PATCH v2] RISC-V: Don't trust V from the riscv,isa DT property on T-Head CPUs

[Conor Dooley]

On Thu, Jul 13, 2023 at 06:36:56PM +0100, Conor Dooley wrote:
> On Fri, Jul 14, 2023 at 01:12:32AM +0800, Jisheng Zhang wrote:
> > On Thu, Jul 13, 2023 at 06:04:22PM +0100, Conor Dooley wrote:
> > > Jumping on top of Palmer's reply cos I had already started replying...
> > > On Thu, Jul 13, 2023 at 09:56:34AM -0700, Palmer Dabbelt wrote:
> > > > On Thu, 13 Jul 2023 09:36:49 PDT (-0700), jszhang at kernel.org wrote:
> > > > > On Wed, Jul 12, 2023 at 06:48:02PM +0100, Conor Dooley wrote:

> > > > > this patch is provided, but can we mitigate the situation by carefully
> > > > > review the DTs? Per my understanding, dts is also part of linux kernel.
> > > > 
> > > > That would break compatibility with existing firmware.  It's certainly
> > > > something that has happened before, but we try to avoid it where possible.
> > > 
> > > (Mostly in reply to Jisheng again)
> > > Sure, some devicetrees are part of the kernel, but not all are - they may
> > > be passed up from U-Boot or OpenSBI etc & contain "v" in riscv,isa.
> > 
> > If so this looks like a bug of u-boot and opensbi.
> > 
> > PS: does u-boot/opensbi modify "riscv,isa" property dynamically? Or
> > there's below usage case:
> > mainline linux kernel + dtb which is built from u-boot/opensbi source
> > code rather than linux kernel.
> 
> Its the latter I am thinking of. If someone wants to go and double check
> that there are no vendors shipping T-Head cores with firmware that
> behaves that way, then the patch could I suppose be dropped.

I don't have one (yet), what is the boot flow in that regard with the
vendor shipped software on the lichee pi4a?
The D1 from the factory is a mess & I use Samuel's firmware/bootloaders,
so it is well behaved :)
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