[PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI

[Palmer Dabbelt]

On Tue, 11 Jul 2023 15:52:56 PDT (-0700), Conor Dooley wrote:
> On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
>> ACPI ISA strings are based on a specification after Zicsr and Zifencei
>> were split out of I, so we shouldn't be treating them as part of I.  We
>> haven't release an ACPI-based kernel yet, so we don't need to worry
>> about compatibility with the old ISA strings.
>> 
>> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
>
> I think, if anything, this is actually:
> Fixes: 07edc32779e3 ("RISC-V: always report presence of extensions formerly part of the base ISA")
>
> Although my rationale was that if we get as far as here, then Zicsr and
> Zifencei are going to be enabled anyway so there is no harm in setting
> it for both. I probably should have been less of a cute hoor though.
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

I think there's no way to get here without the extensions, not 100% sure 
though.  I'm mainly trying to avoid going down the same rabbit hole of 
ISA string compatibility hacks in ACPI that we have for DT, though -- 
I'm sure we'll end up with a mess as soon as we release, but might as 
well catch as much as we can.

>
> Cheers,
> Conor.
>
>> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
>> ---
>>  arch/riscv/kernel/cpufeature.c | 9 ++-------
>>  1 file changed, 2 insertions(+), 7 deletions(-)
>> 
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index bdcf460ea53d..a8f66c015229 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
>>  #undef SET_ISA_EXT_MAP
>>  		}
>>  
>> -		/*
>> -		 * Linux requires the following extensions, so we may as well
>> -		 * always set them.
>> -		 */
>> -		set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
>> -		set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
>> -
>>  		/*
>>  		 * These ones were as they were part of the base ISA when the
>>  		 * port & dt-bindings were upstreamed, and so can be set
>>  		 * unconditionally where `i` is in riscv,isa on DT systems.
>>  		 */
>>  		if (acpi_disabled) {
>> +			set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
>> +			set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
>>  			set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
>>  			set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
>>  		}
>> -- 
>> 2.40.1
>> 
>> 
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