[PATCH v13 1/2] pwm: add microchip soft ip corePWM driver
Uwe Kleine-König
u.kleine-koenig at pengutronix.de
Tue Jan 10 14:48:05 PST 2023
Hello Conor,
On Wed, Dec 21, 2022 at 11:29:12AM +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> Add a driver that supports the Microchip FPGA "soft" PWM IP core.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> drivers/pwm/Kconfig | 10 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-microchip-core.c | 436 +++++++++++++++++++++++++++++++
> 3 files changed, 447 insertions(+)
> create mode 100644 drivers/pwm/pwm-microchip-core.c
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index dae023d783a2..f42756a014ed 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -393,6 +393,16 @@ config PWM_MEDIATEK
> To compile this driver as a module, choose M here: the module
> will be called pwm-mediatek.
>
> +config PWM_MICROCHIP_CORE
> + tristate "Microchip corePWM PWM support"
> + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
> + depends on HAS_IOMEM && OF
> + help
> + PWM driver for Microchip FPGA soft IP core.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-microchip-core.
> +
> config PWM_MXS
> tristate "Freescale MXS PWM support"
> depends on ARCH_MXS || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 7bf1a29f02b8..a65625359ece 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -34,6 +34,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
> obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
> obj-$(CONFIG_PWM_MESON) += pwm-meson.o
> obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
> +obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
> obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
> obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
> obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
> diff --git a/drivers/pwm/pwm-microchip-core.c b/drivers/pwm/pwm-microchip-core.c
> new file mode 100644
> index 000000000000..047fa708b9fc
> --- /dev/null
> +++ b/drivers/pwm/pwm-microchip-core.c
> @@ -0,0 +1,436 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * corePWM driver for Microchip "soft" FPGA IP cores.
> + *
> + * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
> + * Author: Conor Dooley <conor.dooley at microchip.com>
> + * Documentation:
> + * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
> + *
> + * Limitations:
> + * - If the IP block is configured without "shadow registers", all register
> + * writes will take effect immediately, causing glitches on the output.
> + * If shadow registers *are* enabled, a write to the "SYNC_UPDATE" register
> + * notifies the core that it needs to update the registers defining the
> + * waveform from the contents of the "shadow registers".
> + * - The IP block has no concept of a duty cycle, only rising/falling edges of
> + * the waveform. Unfortunately, if the rising & falling edges registers have
> + * the same value written to them the IP block will do whichever of a rising
> + * or a falling edge is possible. I.E. a 50% waveform at twice the requested
> + * period. Therefore to get a 0% waveform, the output is set the max high/low
> + * time depending on polarity.
> + * - The PWM period is set for the whole IP block not per channel. The driver
> + * will only change the period if no other PWM output is enabled.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/ktime.h>
> +#include <linux/math.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +
> +#define PREG_TO_VAL(PREG) ((PREG) + 1)
> +
> +#define MCHPCOREPWM_PRESCALE_MAX 0x100
> +#define MCHPCOREPWM_PERIOD_STEPS_MAX 0xff
> +#define MCHPCOREPWM_PERIOD_MAX 0xff00
> +
> +#define MCHPCOREPWM_PRESCALE 0x00
> +#define MCHPCOREPWM_PERIOD 0x04
> +#define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */
> +#define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x88 */
> +#define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8c */
> +#define MCHPCOREPWM_SYNC_UPD 0xe4
> +#define MCHPCOREPWM_TIMEOUT_MS 100u
> +
> +struct mchp_core_pwm_chip {
> + struct pwm_chip chip;
> + struct clk *clk;
> + void __iomem *base;
> + struct mutex lock; /* protect the shared period */
> + ktime_t update_timestamp;
> + u32 sync_update_mask;
> + u16 channel_enabled;
> +};
> +
> +static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip)
> +{
> + return container_of(chip, struct mchp_core_pwm_chip, chip);
> +}
> +
> +static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
> + bool enable, u64 period)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + u8 channel_enable, reg_offset, shift;
> +
> + /*
> + * There are two adjacent 8 bit control regs, the lower reg controls
> + * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg
> + * and if so, offset by the bus width.
> + */
> + reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
> + shift = pwm->hwpwm & 7;
> +
> + channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
> + channel_enable &= ~(1 << shift);
> + channel_enable |= (enable << shift);
> +
> + writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
> + mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
> + mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
> +
> + /*
> + * Notify the block to update the waveform from the shadow registers.
> + * The updated values will not appear on the bus until they have been
> + * applied to the waveform at the beginning of the next period.
> + * This is a NO-OP if the channel does not have shadow registers.
> + */
> + if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))
> + mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);
> +}
> +
> +static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm,
> + unsigned int channel)
> +{
> + /*
> + * If a shadow register is used for this PWM channel, and iff there is
> + * a pending update to the waveform, we must wait for it to be applied
> + * before attempting to read its state. Reading the registers yields
> + * the currently implemented settings & the new ones are only readable
> + * once the current period has ended.
> + */
> +
> + if (mchp_core_pwm->sync_update_mask & (1 << channel)) {
> + ktime_t current_time = ktime_get();
> + s64 remaining_ns;
> + u32 delay_us;
> +
> + remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,
> + current_time));
> +
> + /*
> + * If the update has gone through, don't bother waiting for
> + * obvious reasons. Otherwise wait around for an appropriate
> + * amount of time for the update to go through.
> + */
> + if (remaining_ns <= 0)
> + return;
> +
> + delay_us = DIV_ROUND_UP_ULL(remaining_ns, NSEC_PER_USEC);
> + if ((delay_us / 1000) > MAX_UDELAY_MS)
> + msleep(delay_us / 1000 + 1);
Is this better than
msleep(DIV_ROUND_UP(delay_us, 1000);
? Also I wonder about your usage of MAX_UDELAY_MS. This is about
udelay() but you're using usleep_range()?
> + else
> + usleep_range(delay_us, delay_us * 2);
I wonder if there isn't a function that implements something like
wait_until(mchp_core_pwm->update_timestamp);
which would be a bit nicer than doing this by hand. Maybe fsleep()?
> + }
> +}
> +
> +[...]
> +
> +static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state, u64 duty_steps,
> + u8 period_steps)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + u8 posedge, negedge;
> + u8 period_steps_val = PREG_TO_VAL(period_steps);
> +
> + /*
> + * Setting posedge == negedge doesn't yield a constant output,
> + * so that's an unsuitable setting to model duty_steps = 0.
> + * In that case set the unwanted edge to a value that never
> + * triggers.
> + */
> + if (state->polarity == PWM_POLARITY_INVERSED) {
> + negedge = !duty_steps ? period_steps_val : 0u;
IMHO
negedge = duty_steps ? 0 : period_steps_val;
is a bit easier to parse.
> + posedge = duty_steps;
> + } else {
> + posedge = !duty_steps ? period_steps_val : 0u;
> + negedge = duty_steps;
> + }
The following code is equivalent:
u8 first_edge = 0, second_edge = duty_steps;
/*
* Setting posedge == negedge doesn't yield a constant output,
* so that's an unsuitable setting to model duty_steps = 0.
* In that case set the unwanted edge to a value that never
* triggers.
*/
if (duty_steps == 0)
first_edge = period_steps_val;
if (state->polarity == PWM_POLARITY_INVERSED) {
negedge = first_edge;
posedge = second_edge;
} else {
posedge = first_edge;
negedge = second_edge;
}
I'm not sure if it's easier to understand. What do you think?
> + writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
> + writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
> +}
> +
> +static void mchp_core_pwm_calc_period(const struct pwm_state *state, unsigned long clk_rate,
> + u16 *prescale, u8 *period_steps)
> +{
> + u64 tmp;
> +
> + /*
> + * Calculate the period cycles and prescale values.
> + * The registers are each 8 bits wide & multiplied to compute the period
> + * using the formula:
> + * (clock_period) * (prescale + 1) * (period_steps + 1)
> + * so the maximum period that can be generated is 0x10000 times the
> + * period of the input clock.
> + * However, due to the design of the "hardware", it is not possible to
> + * attain a 100% duty cycle if the full range of period_steps is used.
> + * Therefore period_steps is restricted to 0xFE and the maximum multiple
> + * of the clock period attainable is 0xFF00.
> + */
> + tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
> +
> + /*
> + * The hardware adds one to the register value, so decrement by one to
> + * account for the offset
> + */
> + if (tmp >= MCHPCOREPWM_PERIOD_MAX) {
> + *prescale = MCHPCOREPWM_PRESCALE_MAX - 1;
> + *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX - 1;
> +
> + return;
> + }
> +
> + *prescale = div_u64(tmp, MCHPCOREPWM_PERIOD_STEPS_MAX);
> + /* PREG_TO_VAL() can produce a value larger than UINT8_MAX */
> + *period_steps = div_u64(tmp, PREG_TO_VAL(*prescale)) - 1;
This looks wrong, but I didn't think long about that. Did we discuss
this already and/or are you sure this is correct?
(We have:
(prescale + 1) * (period_steps + 1)
period = ------------------------------------
clk_rate
You calculate
period * clk_rate
prescale = -------------------
NSEC_PER_SEC * 0xff
period * clk_rate
period_steps = ----------------------------- - 1
NSEC_PER_SEC * (prescale + 1)
assuming exact arithmetic putting these into the above equation we get:
period * clk_rate period * clk_rate
(------------------- + 1) * (-----------------------------) / clk_rate
NSEC_PER_SEC * 0xff NSEC_PER_SEC * (prescale + 1)
and then substituting prescale this doesn't resolve to period, does it?
Correct me if I'm wrong.)
> +}
> +
> +static inline void mchp_core_pwm_apply_period(struct mchp_core_pwm_chip *mchp_core_pwm,
> + u8 prescale, u8 period_steps)
> +{
> + writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
> + writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
> +}
There is only one caller for this two-line function. I suggest to unroll it?
> [...]
> +static int mchp_core_pwm_probe(struct platform_device *pdev)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm;
> + struct resource *regs;
> + int ret;
> +
> + mchp_core_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_core_pwm), GFP_KERNEL);
> + if (!mchp_core_pwm)
> + return -ENOMEM;
> +
> + mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
> + if (IS_ERR(mchp_core_pwm->base))
> + return PTR_ERR(mchp_core_pwm->base);
> +
> + mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
> + if (IS_ERR(mchp_core_pwm->clk))
> + return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),
> + "failed to get PWM clock\n");
> +
> + if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask",
> + &mchp_core_pwm->sync_update_mask))
> + mchp_core_pwm->sync_update_mask = 0;
> +
> + mutex_init(&mchp_core_pwm->lock);
> +
> + mchp_core_pwm->chip.dev = &pdev->dev;
> + mchp_core_pwm->chip.ops = &mchp_core_pwm_ops;
> + mchp_core_pwm->chip.npwm = 16;
> +
> + mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));
> + mchp_core_pwm->channel_enabled |=
> + readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;
> +
> + ret = devm_pwmchip_add(&pdev->dev, &mchp_core_pwm->chip);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
> +
> + /*
> + * Enabled synchronous update for channels with shadow registers
> + * enabled. For channels without shadow registers, this has no effect
> + * at all so is unconditionally enabled.
> + */
> + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
> + mchp_core_pwm->update_timestamp = ktime_get();
This needs to be done before devm_pwmchip_add().
> +
> + return 0;
> +}
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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