[PATCH v3 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2
Conor Dooley
conor at kernel.org
Mon Jan 9 10:02:28 PST 2023
Hey folks,
On Tue, Jan 10, 2023 at 12:52:49AM +0800, Jia Jie Ho wrote:
> Adding StarFive TRNG controller node to VisionFive 2 SoC.
>
> Co-developed-by: Jenny Zhang <jenny.zhang at starfivetech.com>
> Signed-off-by: Jenny Zhang <jenny.zhang at starfivetech.com>
> Signed-off-by: Jia Jie Ho <jiajie.ho at starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 4ac159d79d66..3c29e0bc6246 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -455,5 +455,15 @@ uart5: serial at 12020000 {
> reg-shift = <2>;
> status = "disabled";
> };
> +
> + rng: rng at 1600c000 {
> + compatible = "starfive,jh7110-trng";
> + reg = <0x0 0x1600C000 0x0 0x4000>;
> + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
Which clock source is this? I see syscrg and aoncrg in the v3
devicetree:
https://lore.kernel.org/linux-riscv/20221220011247.35560-7-hal.feng@starfivetech.com/
Have a missed a patchset which adds support for this particular clock
controller? At the very least, I don't think one has reached the
linux-riscv mailing list.
The clock driver patchset only has aoncrg & syscrg:
https://lore.kernel.org/linux-riscv/20221220005054.34518-1-hal.feng@starfivetech.com/
> + clock-names = "hclk", "ahb";
> + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> + interrupts = <30>;
> + };
> };
> };
Thanks,
Conor.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 228 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-riscv/attachments/20230109/7f178362/attachment.sig>
More information about the linux-riscv
mailing list