[PATCH v3 6/7] riscv: dts: starfive: jh7110: Add syscon nodes
Xingyu Wu
xingyu.wu at starfivetech.com
Thu Apr 13 19:41:56 PDT 2023
From: William Qiu <william.qiu at starfivetech.com>
Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc.
Signed-off-by: William Qiu <william.qiu at starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing at canonical.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..f271c3184d3a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,11 @@ i2c2: i2c at 10050000 {
status = "disabled";
};
+ stg_syscon: syscon at 10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
uart3: serial at 12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -457,6 +462,11 @@ syscrg: clock-controller at 13020000 {
#reset-cells = <1>;
};
+ sys_syscon: syscon at 13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+ reg = <0x0 0x13030000 0x0 0x1000>;
+ };
+
sysgpio: pinctrl at 13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
@@ -486,6 +496,11 @@ aoncrg: clock-controller at 17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon at 17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ };
+
aongpio: pinctrl at 17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
--
2.25.1
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