[PATCH v6 4/6] RISC-V: hwprobe: Support probing of misaligned access performance

[Conor Dooley]

On Fri, Apr 07, 2023 at 04:11:01PM -0700, Evan Green wrote:
> This allows userspace to select various routines to use based on the
> performance of misaligned access on the target hardware.
> 
> Rather than adding DT bindings, this change taps into the alternatives
> mechanism used to probe CPU errata. Add a new function pointer alongside
> the vendor-specific errata_patch_func() that probes for desirable errata
> (otherwise known as "features"). Unlike the errata_patch_func(), this
> function is called on each CPU as it comes up, so it can save
> feature information per-CPU.
> 
> The T-head C906 has fast unaligned access, both as defined by GCC [1],
> and in performing a basic benchmark, which determined that byte copies
> are >50% slower than a misaligned word copy of the same data size (source
> for this test at [2]):
> 
> bytecopy size f000 count 50000 offset 0 took 31664899 us
> wordcopy size f000 count 50000 offset 0 took 5180919 us
> wordcopy size f000 count 50000 offset 1 took 13416949 us
> 
> [1] https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.cc#L353
> [2] https://pastebin.com/EPXvDHSW
> 
> Co-developed-by: Palmer Dabbelt <palmer at rivosinc.com>
> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
> Signed-off-by: Evan Green <evan at rivosinc.com>
> Reviewed-by: Heiko Stuebner <heiko.stuebner at vrull.eu>
> Tested-by: Heiko Stuebner <heiko.stuebner at vrull.eu>

I think I had given you an R-b a few versions back, guess it was dropped
due to changes or w/e :)

Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

Perhaps at some point the "errata" naming of those files should change,
but today is not that day.

Cheers,
Conor.
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