[PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC

[Mason Huo]

Add the operating-points-v2 to support cpu scaling
on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.

Signed-off-by: Mason Huo <mason.huo at starfivetech.com>
---
 .../jh7110-starfive-visionfive-2.dtsi         | 25 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 25 +++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index df582bddae4b..ae446b268e78 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -228,3 +228,28 @@ &uart0 {
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&U74_1 {
+	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
+	clock-names = "cpu";
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&U74_2 {
+	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
+	clock-names = "cpu";
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&U74_3 {
+	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
+	clock-names = "cpu";
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&U74_4 {
+	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
+	clock-names = "cpu";
+	cpu-supply = <&reg_dcdc2>;
+};
+
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..c867f968d054 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,7 @@ U74_1: cpu at 1 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
 
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -79,6 +80,7 @@ U74_2: cpu at 2 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
 
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -105,6 +107,7 @@ U74_3: cpu at 3 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
 
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -131,6 +134,7 @@ U74_4: cpu at 4 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
 
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -164,6 +168,27 @@ core4 {
 		};
 	};
 
+	cpu_opp: opp-table-0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+			opp-375000000 {
+					opp-hz = /bits/ 64 <375000000>;
+					opp-microvolt = <800000>;
+			};
+			opp-500000000 {
+					opp-hz = /bits/ 64 <500000000>;
+					opp-microvolt = <800000>;
+			};
+			opp-750000000 {
+					opp-hz = /bits/ 64 <750000000>;
+					opp-microvolt = <800000>;
+			};
+			opp-1500000000 {
+					opp-hz = /bits/ 64 <1500000000>;
+					opp-microvolt = <1040000>;
+			};
+	};
+
 	gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 		compatible = "fixed-clock";
 		clock-output-names = "gmac0_rgmii_rxin";
-- 
2.39.2