[PATCH] riscv: add icache flush for nommu sigreturn trampoline
Mathis Salmen
mathis.salmen at matsal.de
Wed Apr 5 17:11:04 PDT 2023
In a NOMMU kernel, sigreturn trampolines are generated on the user
stack by setup_rt_frame. Currently, these trampolines are not instruction
fenced, thus their visibility to ifetch is not guaranteed.
This patch adds a flush_icache_range in setup_rt_frame to fix this
problem.
Signed-off-by: Mathis Salmen <mathis.salmen at matsal.de>
---
arch/riscv/kernel/signal.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index bfb2afa41..548703230 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -19,6 +19,7 @@
#include <asm/signal32.h>
#include <asm/switch_to.h>
#include <asm/csr.h>
+#include <asm/cacheflush.h>
extern u32 __user_rt_sigreturn[2];
@@ -209,6 +210,10 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
if (copy_to_user(&frame->sigreturn_code, __user_rt_sigreturn,
sizeof(frame->sigreturn_code)))
return -EFAULT;
+ /* Make sure the two instructions are pushed to icache. */
+ flush_icache_range((uintptr_t)&frame->sigreturn_code,
+ (uintptr_t)&frame->sigreturn_code + sizeof(frame->sigreturn_code));
+
regs->ra = (unsigned long)&frame->sigreturn_code;
#endif /* CONFIG_MMU */
--
2.40.0
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