[PATCH v3 2/8] RISC-V: Detect AIA CSRs from ISA string
Conor Dooley
conor.dooley at microchip.com
Mon Apr 3 02:39:46 PDT 2023
On Mon, Apr 03, 2023 at 03:03:04PM +0530, Anup Patel wrote:
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 59d58ee0f68d..1b13a5823b90 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -221,8 +221,10 @@ void __init riscv_fill_hwcap(void)
> }
> } else {
> /* sorted alphabetically */
^^^^^^^^^^^^^^^^^^^^^
> + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
> SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
> + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
This entry has been added in an incorrect order chief :/
> SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
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