[PATCH v2 09/14] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

[Hal Feng]

On Fri, 25 Nov 2022 14:41:12 +0800, Hal Feng wrote:
> On Mon, 21 Nov 2022 09:47:08 +0100, Krzysztof Kozlowski wrote:
> > On 18/11/2022 02:06, Hal Feng wrote:
> > > From: Emil Renner Berthing <kernel at esmil.dk>
> > > 
> > > Add bindings for the system clock and reset generator (SYSCRG) on the
> > > JH7110 RISC-V SoC by StarFive Ltd.
> > > 
> > > Signed-off-by: Emil Renner Berthing <kernel at esmil.dk>
> > > Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
> > 
> > Binding headers are coming with the file bringing bindings for the
> > device, so you need to squash patches.
> 
> As we discussed in patch 7, could I merge patch 7, 8, 9, 10 and add the
> following files in one commit?
> 
> include/dt-bindings/clock/starfive,jh7110-crg.h
> include/dt-bindings/reset/starfive,jh7110-crg.h
> Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml

Hi, Krzysztof,

Could you please give me some suggestions?

Best regards,
Hal

> 
> > 
> > > ---
> > >  .../clock/starfive,jh7110-syscrg.yaml         | 80 +++++++++++++++++++
> > >  MAINTAINERS                                   |  2 +-
> > >  2 files changed, 81 insertions(+), 1 deletion(-)
> > >  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>