[PATCH] RISC-V: enable sparsemem by default for defconfig

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer at rivosinc.com>:

On Fri, 21 Oct 2022 17:00:30 +0100 you wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> on an arch level, RISC-V defaults to FLATMEM. On PolarFire SoC, the
> memory layout is almost always sparse, with a maximum of 1 GiB at
> 0x8000_0000 & a possible 16 GiB range at 0x10_0000_0000. The Icicle kit,
> for example, has 2 GiB of DDR - so there's a big hole in the memory map
> between the two gigs. Prior to v6.1-rc1, boot times from defconfig
> builds were pretty bad on Icicle but enabling sparsemem would fix those
> issues. As of v6.1-rc1, the Icicle kit no longer boots from defconfig
> builds with the in-kernel devicetree. A change to the memory map
> resulted in a futher "sparse-ification", producing a splat on boot:
> 
> [...]

Here is the summary with links:
  - RISC-V: enable sparsemem by default for defconfig
    https://git.kernel.org/riscv/c/41555cc9e2e9

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html