[PATCH] riscv: Fix NR_CPUS range conditions

[Conor Dooley]

On Sat, Nov 26, 2022 at 12:15:56AM -0600, Samuel Holland wrote:
> The conditions reference the symbol SBI_V01, which does not exist. The
> correct symbol is RISCV_SBI_V01.

Huh, good spot.
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

> 
> Fixes: e623715f3d67 ("RISC-V: Increase range and default value of NR_CPUS")
> Signed-off-by: Samuel Holland <samuel at sholland.org>
> ---
> 
>  arch/riscv/Kconfig | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index fec54872ab45..acbfe34c6a00 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -319,9 +319,9 @@ config SMP
>  config NR_CPUS
>  	int "Maximum number of CPUs (2-512)"
>  	depends on SMP
> -	range 2 512 if !SBI_V01
> -	range 2 32 if SBI_V01 && 32BIT
> -	range 2 64 if SBI_V01 && 64BIT
> +	range 2 512 if !RISCV_SBI_V01
> +	range 2 32 if RISCV_SBI_V01 && 32BIT
> +	range 2 64 if RISCV_SBI_V01 && 64BIT
>  	default "32" if 32BIT
>  	default "64" if 64BIT
>  
> -- 
> 2.37.4
>