[PATCH 0/2] riscv,isa fixups
Conor Dooley
conor.dooley at microchip.com
Thu Nov 24 05:04:39 PST 2022
I noticed today while looking at the isa manual that I had not accounted
for another couple of edge cases with my regex. As before, I think
attempting to validate the canonical order for multiletter stuff makes
no sense - but we should totally try to avoid false-positives for
combinations that are known to be valid.
Thanks,
Conor.
CC: Conor Dooley <conor at kernel.org>
CC: Rob Herring <robh+dt at kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
CC: Paul Walmsley <paul.walmsley at sifive.com>
CC: Palmer Dabbelt <palmer at dabbelt.com>
CC: Albert Ou <aou at eecs.berkeley.edu>
CC: Heiko Stuebner <heiko at sntech.de>
CC: Andrew Jones <ajones at ventanamicro.com>
CC: Guo Ren <guoren at kernel.org>
CC: linux-riscv at lists.infradead.org
CC: devicetree at vger.kernel.org
CC: linux-kernel at vger.kernel.org
Conor Dooley (2):
dt-bindings: riscv: fix underscore requirement for addtional standard
extensions
dt-bindings: riscv: fix single letter canonical order
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.38.1
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