RISC-V SoC Drivers for v6.2

[Conor Dooley]

Hey Arnd,

Same stuff applies here: lmk if there's something you'd rather see changed.
Perhaps you'd prefer to see PRs per vendor? Although I think that's less
likely to matter here than in the DT stuff. Again, I'll try to get the PR
out a bit earlier next time.

Not too much to see here, Yang Yingliang has added some error handling
to the setup of the driver that reports SiFive cache topology
information. I've put it on -next given how far we are in the release
cycle, feel free to put it on fixes if you disagree :)

Thanks,
Conor.

The following changes since commit 9abf2313adc1ca1b6180c508c25f22f9395cc780:

  Linux 6.1-rc1 (2022-10-16 15:36:24 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-soc-for-v6.2-mw0

for you to fetch changes up to 8fbf94fea0b4e187ca9100936c5429f96b8a4e44:

  soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init() (2022-11-09 22:01:31 +0000)

----------------------------------------------------------------
RISC-V SoC drivers for v6.2

SiFive:
- add probe error handling to the ccache driver

----------------------------------------------------------------
Yang Yingliang (3):
      soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()
      soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
      soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()

 drivers/soc/sifive/sifive_ccache.c | 33 +++++++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 8 deletions(-