[PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem

[Conor Dooley]

On Tue, Nov 08, 2022 at 03:59:06PM +0000, Sudeep Holla wrote:
> On Tue, Nov 08, 2022 at 02:07:41PM +0000, Conor Dooley wrote:
> > On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > > Riscv's implementation of init_of_cache_level() is following
> > 
> > heh, "Riscv" always looks a bit odd!
> > Code movement looks fine, nothing surface level is broken on RISC-V.
> > Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
> >
> Thanks for the review and testing. I was planning to ask Pierre to cc you
> next time but you seem to have covered that for me :).

Ye no worries.
Feel free to add some sort of "R: Conor Dooley <conor at kernel.org>" entry
where appropriate if you want to make sure I'll take a look - but I
should see it anyway if it goes to the riscv list.
Up to you.