[PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Geert Uytterhoeven]

On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
>
> Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - PLIC
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> v4 -> v5
> * Fixed riscv,ndev value (should be 511)
> * Reworked completely (sort of new patch)

Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds