Should we merge arch/riscv/boot/dts via the SOC tree?

[Conor Dooley]

On Tue, Nov 08, 2022 at 02:42:16PM +0100, Arnd Bergmann wrote:
> On Tue, Nov 8, 2022, at 14:32, Conor Dooley wrote:
> > On Tue, Nov 08, 2022 at 01:51:37PM +0100, Arnd Bergmann wrote:
> >> On Mon, Nov 7, 2022, at 19:31, Conor Dooley wrote:
> >> 
> >> I'd probably make separate entries here, at least for the
> >> drivers/soc/microchip directory, I can see that being shared with
> >> architectures other than RISC-V in the future
> >
> > (Added Nicolas to CC so that he's in the loop)
> > Uh sure. It'd crossed my mind, but I filed it away in the "may happen
> > some day" category. The arm stuff is going via the atmel directory at
> > the moment so I was operating on the basis of "do it this way until
> > something changes".
> > Splitting is fine by me. As things stand, anything drivers/soc/microchip
> > already CCs the linux-riscv list so maybe that can change alongside
> > this.
> 
> Right, but I suppose there is a good chance of having more
> crossover between microchip riscv/arm/mips drivers in the
> future, and others like Renesas already have drivers/soc/
> subdirectories that are shared.

Aye, I'll make it separate. Will make the existing entry that references
the directory more specific too (whitespace damaged):
diff --git a/MAINTAINERS b/MAINTAINERS
index 046ff06ff97f..5b48eea5e9bb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17749,7 +17749,7 @@ F:      drivers/mailbox/mailbox-mpfs.c
 F:     drivers/pci/controller/pcie-microchip-host.c
 F:     drivers/reset/reset-mpfs.c
 F:     drivers/rtc/rtc-mpfs.c
-F:     drivers/soc/microchip/
+F:     drivers/soc/microchip/mpfs-sys-controller.c
 F:     drivers/spi/spi-microchip-core-qspi.c
 F:     drivers/spi/spi-microchip-core.c
 F:     drivers/usb/musb/mpfs.c


> > The one I was wondering about but forgot to mention was:
> > Documentation/devicetree/bindings/riscv/
> >
> > It's mostly definitions of cpu, soc and board compatibles, so I figure
> > it could go with the dt stuff - and it's covered by the generic RISC-V
> > entry for the changes that reflect extensions etc.
> 
> Right, that works.

Cool.

I assume your ommission of the SiFive bit from this mail means you're
happy enough with it?

Thanks,
Conor.