[PATCH v3 1/4] RISC-V: Add SSTC extension CSR details

[Anup Patel]

On Wed, Apr 27, 2022 at 12:23 AM Atish Patra <atishp at rivosinc.com> wrote:
>
> This patch just introduces the required CSR fields related to the
> SSTC extension.
>
> Signed-off-by: Atish Patra <atishp at rivosinc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  arch/riscv/include/asm/csr.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index e935f27b10fd..10f4e1c36908 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -227,6 +227,9 @@
>  #define CSR_SIP                        0x144
>  #define CSR_SATP               0x180
>
> +#define CSR_STIMECMP           0x14D
> +#define CSR_STIMECMPH          0x15D
> +
>  #define CSR_VSSTATUS           0x200
>  #define CSR_VSIE               0x204
>  #define CSR_VSTVEC             0x205
> @@ -236,6 +239,8 @@
>  #define CSR_VSTVAL             0x243
>  #define CSR_VSIP               0x244
>  #define CSR_VSATP              0x280
> +#define CSR_VSTIMECMP          0x24D
> +#define CSR_VSTIMECMPH         0x25D
>
>  #define CSR_HSTATUS            0x600
>  #define CSR_HEDELEG            0x602
> @@ -251,6 +256,8 @@
>  #define CSR_HTINST             0x64a
>  #define CSR_HGATP              0x680
>  #define CSR_HGEIP              0xe12
> +#define CSR_HENVCFG            0x60A
> +#define CSR_HENVCFGH           0x61A
>
>  #define CSR_MSTATUS            0x300
>  #define CSR_MISA               0x301
> @@ -312,6 +319,10 @@
>  #define IE_TIE         (_AC(0x1, UL) << RV_IRQ_TIMER)
>  #define IE_EIE         (_AC(0x1, UL) << RV_IRQ_EXT)
>
> +/* ENVCFG related bits */
> +#define HENVCFG_STCE   63
> +#define HENVCFGH_STCE  31
> +
>  #ifndef __ASSEMBLY__
>
>  #define csr_swap(csr, val)                                     \
> --
> 2.25.1
>