[PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers

[Palmer Dabbelt]

On Mon, 23 May 2022 04:42:53 PDT (-0700), Conor.Dooley at microchip.com wrote:
> On 05/05/2022 11:55, Conor Dooley wrote:
>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
>> Daire is the author of the clock & PCI drivers, so add him as a
>> maintainer in place of Lewis.
>> 
>> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> 
> Hey Palmer,
> I know youre busy etc but just a reminder :)

Sorry, I didn't realize this was aimed at the RISC-V tree.  I'm fine 
taking it, but it seems like these should have gone in along with the 
drivers.

Arnd: maybe this is really an SOC tree sort of thing?  No big deal 
either way on my end, just let me know.

> Thanks,
> Conor.
> 
>> ---
>>   MAINTAINERS | 5 ++++-
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index fd768d43e048..d7602658b0a5 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -16939,12 +16939,15 @@ N:	riscv
>>   K:	riscv
>>   
>>   RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>> -M:	Lewis Hanly <lewis.hanly at microchip.com>
>>   M:	Conor Dooley <conor.dooley at microchip.com>
>> +M:	Daire McNamara <daire.mcnamara at microchip.com>
>>   L:	linux-riscv at lists.infradead.org
>>   S:	Supported
>>   F:	arch/riscv/boot/dts/microchip/
>> +F:	drivers/char/hw_random/mpfs-rng.c
>> +F:	drivers/clk/microchip/clk-mpfs.c
>>   F:	drivers/mailbox/mailbox-mpfs.c
>> +F:	drivers/pci/controller/pcie-microchip-host.c
>>   F:	drivers/soc/microchip/
>>   F:	include/soc/microchip/mpfs.h
>>   
>