[PATCH] arch/riscv: Add Zihintpause extension support
Dao Lu
daolu at rivosinc.com
Thu May 12 11:06:53 PDT 2022
Resending this one as it was blocked.
Thanks Heiko.
Made the following changes.
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 327c19507dbb..f42c7d983d39 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -216,9 +216,8 @@ void __init riscv_fill_hwcap(void)
}
- if (__riscv_isa_extension_available(riscv_isa,
RISCV_ISA_EXT_ZIHINTPAUSE)) {
+ if (__riscv_isa_extension_available(riscv_isa,
RISCV_ISA_EXT_ZIHINTPAUSE))
static_branch_enable(&riscv_pause_available);
- }
/* We don't support systems with F but without D, so mask those out
* here. */
And will update the commit message when sending out the v2. I will
wait a bit to see if there are more comments.
Regards,
Dao
On Thu, May 12, 2022 at 9:47 AM Dao Lu <daolu at rivosinc.com> wrote:
>
> Thanks Heiko.
>
> Made the following changes.
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 327c19507dbb..f42c7d983d39 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -216,9 +216,8 @@ void __init riscv_fill_hwcap(void)
>
> }
>
> - if (__riscv_isa_extension_available(riscv_isa, RISCV_ISA_EXT_ZIHINTPAUSE)) {
> + if (__riscv_isa_extension_available(riscv_isa, RISCV_ISA_EXT_ZIHINTPAUSE))
> static_branch_enable(&riscv_pause_available);
> - }
>
> /* We don't support systems with F but without D, so mask those out
> * here. */
>
> And will update the commit message when sending out the v2. I will wait a bit to see if there are more comments.
>
> Regards,
> Dao
>
> On Thu, May 12, 2022 at 4:12 AM Heiko Stübner <heiko at sntech.de> wrote:
>>
>> Hi,
>>
>> Am Donnerstag, 12. Mai 2022, 05:30:45 CEST schrieb Dao Lu:
>> > This patch:
>> > 1. Build with _zihintpause if the toolchain has support for it
>> > 2. Detects if the platform supports the extension
>> > 3. Use PAUSE for cpu_relax if both toolchain and the platform support it
>>
>> This simply explains what the patch does, which is also pretty easy to
>> see by just reading the patch, so doesn't provide real additional value.
>>
>> Please use the commit message to provide more background on what
>> you want to achieve. I.e. a short explanation what it is.
>>
>> -----
>> Implement support for the ZiHintPause extension.
>>
>> The PAUSE instruction is a HINT that indicates the current hart’s rate of
>> instruction retirement should be temporarily reduced or paused.
>> -----
>>
>> The second sentence obviously comes directly from the riscv-spec pdf ;-)
>>
>> There is one nit below too and with that fixed
>>
>> Reviewed-by: Heiko Stuebner <heiko at sntech.de>
>>
>> On a Qemu build with your extension patch for it, also
>> Tested-by: Heiko Stuebner <heiko at sntech.de>
>>
>>
>> > Signed-off-by: Dao Lu <daolu at rivosinc.com>
>> > ---
>> > arch/riscv/Makefile | 4 ++++
>> > arch/riscv/include/asm/hwcap.h | 1 +
>> > arch/riscv/include/asm/vdso/processor.h | 19 ++++++++++++++++---
>> > arch/riscv/kernel/cpu.c | 1 +
>> > arch/riscv/kernel/cpufeature.c | 7 +++++++
>> > 5 files changed, 29 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
>> > index 7d81102cffd4..900a8fda1a2d 100644
>> > --- a/arch/riscv/Makefile
>> > +++ b/arch/riscv/Makefile
>> > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
>> > toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
>> > riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
>> >
>> > +# Check if the toolchain supports Zihintpause extension
>> > +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause)
>> > +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause
>> > +
>> > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
>> > KBUILD_AFLAGS += -march=$(riscv-march-y)
>> >
>> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>> > index 0734e42f74f2..caa9ee5459b4 100644
>> > --- a/arch/riscv/include/asm/hwcap.h
>> > +++ b/arch/riscv/include/asm/hwcap.h
>> > @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap;
>> > */
>> > enum riscv_isa_ext_id {
>> > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
>> > + RISCV_ISA_EXT_ZIHINTPAUSE,
>> > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
>> > };
>> >
>> > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
>> > index 134388cbaaa1..106b35ba8cac 100644
>> > --- a/arch/riscv/include/asm/vdso/processor.h
>> > +++ b/arch/riscv/include/asm/vdso/processor.h
>> > @@ -4,15 +4,28 @@
>> >
>> > #ifndef __ASSEMBLY__
>> >
>> > +#include <linux/jump_label.h>
>> > #include <asm/barrier.h>
>> > +#include <asm/hwcap.h>
>> >
>> > +extern struct static_key_false riscv_pause_available;
>> > static inline void cpu_relax(void)
>> > {
>> > + if (!static_branch_likely(&riscv_pause_available)) {
>> > #ifdef __riscv_muldiv
>> > - int dummy;
>> > - /* In lieu of a halt instruction, induce a long-latency stall. */
>> > - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>> > + int dummy;
>> > + /* In lieu of a halt instruction, induce a long-latency stall. */
>> > + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>> > #endif
>> > + } else {
>> > +#ifdef __riscv_zihintpause
>> > + /*
>> > + * Reduce instruction retirement.
>> > + * This assumes the PC changes.
>> > + */
>> > + __asm__ __volatile__ ("pause");
>> > +#endif
>> > + }
>> > barrier();
>> > }
>> >
>> > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
>> > index ccb617791e56..89e563e9c4cc 100644
>> > --- a/arch/riscv/kernel/cpu.c
>> > +++ b/arch/riscv/kernel/cpu.c
>> > @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node)
>> > */
>> > static struct riscv_isa_ext_data isa_ext_arr[] = {
>> > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
>> > + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
>> > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
>> > };
>> >
>> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> > index 1b2d42d7f589..327c19507dbb 100644
>> > --- a/arch/riscv/kernel/cpufeature.c
>> > +++ b/arch/riscv/kernel/cpufeature.c
>> > @@ -24,6 +24,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>> > #ifdef CONFIG_FPU
>> > __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
>> > #endif
>> > +DEFINE_STATIC_KEY_FALSE(riscv_pause_available);
>> > +EXPORT_SYMBOL_GPL(riscv_pause_available);
>> >
>> > /**
>> > * riscv_isa_extension_base() - Get base extension word
>> > @@ -192,6 +194,7 @@ void __init riscv_fill_hwcap(void)
>> > set_bit(*ext - 'a', this_isa);
>> > } else {
>> > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
>> > + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
>> > }
>> > #undef SET_ISA_EXT_MAP
>> > }
>> > @@ -213,6 +216,10 @@ void __init riscv_fill_hwcap(void)
>> >
>> > }
>> >
>> > + if (__riscv_isa_extension_available(riscv_isa, RISCV_ISA_EXT_ZIHINTPAUSE)) {
>> > + static_branch_enable(&riscv_pause_available);
>> > + }
>> > +
>>
>> You don't really need the braces for the single call to static_branch_enable
>>
>>
>> > /* We don't support systems with F but without D, so mask those out
>> > * here. */
>> > if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
>> >
>>
>>
>> Heiko
>>
>>
>>
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