[PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32

[Heiko Stübner]

Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel:
> On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp at rivosinc.com> wrote:
> >
> > Pass the upper half of the initial value of the counter correctly
> > for RV32.
> >
> > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> >
> > Signed-off-by: Atish Patra <atishp at rivosinc.com>
> > ---
> >  drivers/perf/riscv_pmu_sbi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > index a1317a483512..24cea59612be 100644
> > --- a/drivers/perf/riscv_pmu_sbi.c
> > +++ b/drivers/perf/riscv_pmu_sbi.c
> > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
> >                         max_period = riscv_pmu_ctr_get_width_mask(event);
> >                         init_val = local64_read(&hwc->prev_count) & max_period;
> >                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
> > -                                 flag, init_val, 0, 0);
> > +                                 flag, init_val, init_val >> 32, 0);
> 
> This should be under "#if __riscv_xlen == 32".

What's the difference between using CONFIG_32BIT
and checking the __riscv_xlen flag value?

CONFIG_32BIT seems to be a bit the more kernel'ish
way to do this, but it looks like most SBI parts check the
__riscv_xlen instead.


In any case, looking at the opensbi-side of the call,
this fix is abviously correct, so

Reviewed-by: Heiko Stuebner <heiko at sntech.de>