[PATCH v2 2/2] riscv: Don't output a bogus mmu-type on a no MMU kernel

Anup Patel anup at brainfault.org
Mon May 2 05:57:57 PDT 2022


On Mon, May 2, 2022 at 6:20 PM Niklas Cassel <niklas.cassel at wdc.com> wrote:
>
> Currently on a 64-bit kernel built without CONFIG_MMU, /proc/cpuinfo will
> show the current MMU mode as sv57.
>
> While the device tree property "mmu-type" does have a value "riscv,none" to
> describe a CPU without a MMU, since commit 73c7c8f68e72 ("riscv: Use
> pgtable_l4_enabled to output mmu_type in cpuinfo"), we no longer rely on
> device tree to output the MMU mode. (Not even for CONFIG_32BIT.)
>
> Therefore, instead of readding code to look at the "mmu-type" device tree
> property, let's continue with the existing convention to use fixed values
> for configurations where we don't determine the MMU mode at runtime.
>
> Add a new fixed value for !CONFIG_MMU in order to output the correct
> MMU mode in cpuinfo.
>
> Signed-off-by: Niklas Cassel <niklas.cassel at wdc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  arch/riscv/kernel/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index ccb617791e56..ecfb3e85ffb2 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -138,6 +138,7 @@ static void print_mmu(struct seq_file *f)
>  {
>         char sv_type[16];
>
> +#ifdef CONFIG_MMU
>  #if defined(CONFIG_32BIT)
>         strncpy(sv_type, "sv32", 5);
>  #elif defined(CONFIG_64BIT)
> @@ -148,6 +149,9 @@ static void print_mmu(struct seq_file *f)
>         else
>                 strncpy(sv_type, "sv39", 5);
>  #endif
> +#else
> +       strncpy(sv_type, "none", 5);
> +#endif /* CONFIG_MMU */
>         seq_printf(f, "mmu\t\t: %s\n", sv_type);
>  }
>
> --
> 2.35.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



More information about the linux-riscv mailing list