[PATCH 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2

[JiaJie Ho]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Sent: Wednesday, December 21, 2022 5:48 PM
> To: JiaJie Ho <jiajie.ho at starfivetech.com>; Olivia Mackall
> <olivia at selenic.com>; Herbert Xu <herbert at gondor.apana.org.au>; Rob
> Herring <robh+dt at kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt at linaro.org>
> Cc: Emil Renner Berthing <kernel at esmil.dk>; Conor Dooley
> <conor.dooley at microchip.com>; linux-crypto at vger.kernel.org;
> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-
> riscv at lists.infradead.org
> Subject: Re: [PATCH 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2
> 
> > +
> > +		rng: rng at 1600c000 {
> > +			compatible = "starfive,jh7110-trng";
> > +			reg = <0x0 0x1600C000 0x0 0x4000>;
> > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> > +			clock-names = "hclk", "ahb";
> > +			resets = <&stgcrg
> JH7110_STGRST_SEC_TOP_HRESETN>;
> > +			interrupts = <30>;
> > +			status = "okay";
> 
> Drop. It's by default.
> 
I'll fix this in v2.

Thanks,
Jia Jie