[PATCH v3 2/2] dt-bindings: riscv: fix single letter canonical order

[Rob Herring]

On Mon, 05 Dec 2022 17:45:00 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> I used the wikipedia table for ordering extensions when updating the
> pattern here in commit 299824e68bd0 ("dt-bindings: riscv: add new
> riscv,isa strings for emulators").
> 
> Unfortunately that table did not match canonical order, as defined by
> the RISC-V ISA Manual, which defines extension ordering in (what is
> currently) Table 41, "Standard ISA extension names". Fix things up by
> re-sorting v (vector) and adding p (packed-simd) & j (dynamic
> languages). The e (reduced integer) and g (general) extensions are still
> intentionally left out.
> 
> Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> Acked-by: Guo Ren <guoren at kernel.org>
> Reviewed-by: Heiko Stuebner <heiko at sntech.de>
> Reviewed-by: Palmer Dabbelt <palmer at rivosinc.com>
> Acked-by: Palmer Dabbelt <palmer at rivosinc.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh at kernel.org>