[PATCH 1/1] nvme-pci: set virt boundary according to capability

[Keith Busch]

On Tue, Dec 09, 2025 at 01:31:21PM +0200, Max Gurtovoy wrote:
> dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
> 
> and
> 
> lim->dma_alignment = 3;
> 
> to ease the restriction for capable devices with NVME_CTRL_SGLS_BYTE_ALIGNED
> support ?

Yeah, the dma_alignment is the limit you'd need to change. Note, you
can't actually set the dma_alignment to be byte aligned as it's a mask,
so you'd want the value to be 0 to allow any alignment, but the block
layer currently won't let it be 0, so you'd have to set it to 1, for
word alignment.

But I'm surprised to hear of a device that can do byte aligned SGLs, as
PCIe fundamentally can't do byte aligned DMA. It's all dword based, so
if you have a device that does report byte alignment, it's still sending
dwords over the wire. It's just using the "byte enable" fields in the
TLP header to have the receiver strip off preceding and/or trailing
bytes, so it is a bit inefficient way to transfer data.