[PATCH] nvme-pci: fix resume after AER recovery

[Keith Busch]

On Mon, Feb 06, 2023 at 04:42:18PM +0100, Christoph Hellwig wrote:
> On Mon, Feb 06, 2023 at 03:02:20PM +0100, Javier.gonz at samsung.com wrote:
> > Is there a chance we can get a quirk for this for this FW. Seems like an
> > issue on our side that is creating problems.
> 
> So waht would the quirk look like?  This would have to be something in
> the core PCIe code, not NVMe as far as I can tell.

Yeah, I'm assuming it's a PCI level quirk because the remove-rescan was
successful at reinitializing. The remove-rescan should do a very similiar
config space setup and nvme startup as an AER recovery, so I'm guessing this is
a matter of timing. If so, the below is how I'd imagine the quirk may look.

But if this idea isn't successful, it'd be bit a more work to figure out what
sequence this device wants to happen in order to complete recovery.

---
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index fba95486caaf2..f642e7029e0e9 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5054,7 +5054,10 @@ void pci_reset_secondary_bus(struct pci_dev *dev)
 	 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms.  Double
 	 * this to 2ms to ensure that we meet the minimum requirement.
 	 */
-	msleep(2);
+	if (dev->quirks & <NEW_SB_DELAY_QUIRK_BIT>)
+		msleep(100);
+	else
+		msleep(2);
 
 	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
@@ -5066,7 +5069,10 @@ void pci_reset_secondary_bus(struct pci_dev *dev)
 	 * be re-initialized.  PCIe has some ways to shorten this,
 	 * but we don't make use of them yet.
 	 */
-	ssleep(1);
+	if (dev->quirks & <NEW_SB_DELAY_QUIRK_BIT>)
+		ssleep(5);
+	else
+		ssleep(1);
 }
 
 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
--