[PATCH v1 0/4] Add command id quirk for fabrics

[Sagi Grimberg]

>>> 6. This series just extends this quirk for fabrics.
>>
>> I don't think the patchset got rejected, the ask afaict was to document
>> known broken controllers - exactly like pci quirks.
>>
>> Here is the original question from Keith:
>> "Are there really fabrics targets behaving this way, or is this series
>> anticipating they might exist?"
>>
>> I don't think there is any desire to keep any controller that got the
>> spec wrong in this particular case unusable.
> 
> The example I have is the new mlx5 offload for nvme-tcp has HW design 
> that, unfortunately, made an optimization that relies on a indexed CID.
> All the testing was done with Linux kernel's prior to the gen counter 
> change using internal tools, so chips now exist with some performance and
> memory foot print implications when the gen counter is operated.

I see. Well as said, I don't think anyone rejected the proposed
patchset, we were simply looking to understand if this is a real
problem or a theoretical one.

> NVIDIA is committed to NVMe standards compliance and will fix this 
> design in next silicon so no quirks will be needed to get the best 
> performance.

That is great to know.

> I guess we can put this discussion and patch-set aside until we come 
> with some performance impact measurements with the mlx5 offload HW.
> All we know right now is that the new CID algorithm triggers bad 
> performance using our internal simulation.

OK, I think that it will make sense to revisit this with the next
submission of the offload.