[PATCH v9 08/18] spi: cadence-quadspi: add PHY tuning support

[Mark Brown]

On Tue, Aug 25, 2026 at 10:47:27PM +0530, Santhosh Kumar K wrote:
> The Cadence QSPI controller supports a delay-line PHY for high-speed
> operation. Without calibration the PHY is unused and read capture relies
> on a fixed delay, limiting throughput at frequencies above the base
> operating speed.

> Add an execute_tuning callback that performs delay-line calibration using
> a known data pattern written to a dedicated flash region. The pattern is
> either read from a NOR partition identified by the DT property
> spi-phy-pattern-partition, or written to the NAND page cache before
> each calibration read.

>  struct cqspi_flash_pdata {

> +	bool			use_dqs;
> +	bool			use_tuned_phy;

The AM65x has a fun erratum i2189 which mentions that it requires 
disabling DQS for writes:

   https://www.ti.com.cn/lit/er/sprz452i/sprz452i.pdf

which suggests we might need separate controls for read and write
operation.

> +static int cqspi_write_pattern_to_cache(struct cqspi_flash_pdata *f_pdata,
> +					struct spi_mem *mem,
> +					const struct spi_mem_op *write_op)
> +{
> +	struct spi_controller *ctlr = mem->spi->controller;
> +	struct device *dev = &f_pdata->cqspi->pdev->dev;
> +	struct spi_mem_op op = *write_op;
> +	int ret;
> +
> +	op.max_freq = mem->spi->max_speed_hz;
> +	op.data.nbytes = sizeof(phy_tuning_pattern);
> +	op.data.buf.out = phy_tuning_pattern;
> +
> +	ret = ctlr->mem_ops->exec_op(mem, &op);
> +	if (ret) {
> +		dev_err(dev, "Failed to write PHY pattern to cache: %d\n", ret);
> +		return ret;
> +	}
> +	dev_dbg(dev, "PHY pattern (%zu bytes) written to cache\n",
> +		sizeof(phy_tuning_pattern));
> +
> +	return 0;
> +}

spinand_write_page() has a multi-operation sequence, I've not checked if
any fancy flashes with DQS support actually need that.  _read_page()
looks more straightforward.
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