[PATCH v9 2/6] spi: spi-mem: Allow specifying the byte order in Octal DTR mode

[Mark Brown]

On Thu, Jul 18, 2024 at 11:46:10AM +0800, AlvinZhou wrote:
> From: AlvinZhou <alvinzhou at mxic.com.tw>
> 
> From: Tudor Ambarus <tudor.ambarus at linaro.org>
> 
> There are NOR flashes (Macronix) that swap the bytes on a 16-bit
> boundary when configured in Octal DTR mode. The byte order of
> 16-bit words is swapped when read or written in Octal Double
> Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
> modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses

Acked-by: Mark Brown <broonie at kernel.org>
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