[PATCH] mtd: spi-nor: Add support for gd25 and gd55 series chips.

[Renjun Wang]

On 9/7/24 15:04, Christophe JAILLET wrote:
> Le 07/09/2024 à 08:32, Renjun Wang a écrit :
>> Add support for gd25lq255, gd25lb256, gd25lb512m, gd25b512m, gd55b01ge
>> and gd55lb01ge. All these chips are tested on Rockchip boards[1].
>>
>> [1]https://github.com/rockchip-linux/kernel/blob/develop-5.10/drivers/mtd/spi-nor/gigadevice.c 
>>
>>
>> Signed-off-by: Renjun Wang <renjunw0 at foxmail.com>
>> ---
>>   drivers/mtd/spi-nor/gigadevice.c | 43 ++++++++++++++++++++++++++++++++
>>   1 file changed, 43 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/gigadevice.c 
>> b/drivers/mtd/spi-nor/gigadevice.c
>> index ef1edd0add70..f0069a4adbbf 100644
>> --- a/drivers/mtd/spi-nor/gigadevice.c
>> +++ b/drivers/mtd/spi-nor/gigadevice.c
>> @@ -61,6 +61,7 @@ static const struct flash_info 
>> gigadevice_nor_parts[] = {
>>       }, {
>>           .id = SNOR_ID(0xc8, 0x40, 0x19),
>>           .name = "gd25q256",
>> +        .size = SZ_32M,
>
> Hi, just for my understanding, why this change?
>
> If it is a fix, should it be done a separate patch?
> Or should it be mentioned in the commit description?
>
> CJ
>
>>           .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | 
>> SPI_NOR_TB_SR_BIT6,
>>           .fixups = &gd25q256_fixups,
>>           .fixup_flags = SPI_NOR_4B_OPCODES,
>> @@ -82,6 +83,48 @@ static const struct flash_info 
>> gigadevice_nor_parts[] = {
>>           .size = SZ_16M,
>>           .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
>>           .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | 
>> SPI_NOR_QUAD_READ,
>> +    }, {
>> +        .id = SNOR_ID(0xc8, 0x60, 0x19),
>> +        .name = "gd25lq255",
>> +        .size = SZ_32M,
>> +        .flags = SPI_NOR_HAS_LOCK,
>> +        .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | 
>> SPI_NOR_QUAD_READ,
>> +        .fixup_flags = SPI_NOR_4B_OPCODES,
>> +    }, {
>> +        .id = SNOR_ID(0xc8, 0x67, 0x19),
>> +        .name = "gd25lb256",
>> +        .size = SZ_32M,
>> +        .flags = SPI_NOR_HAS_LOCK,
>> +        .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | 
>> SPI_NOR_QUAD_READ,
>> +        .fixup_flags = SPI_NOR_4B_OPCODES,
>> +    }, {
>> +        .id = SNOR_ID(0xc8, 0x67, 0x1a),
>> +        .name = "gd25lb512m",
>> +        .size = SZ_64M,
>> +        .flags = SPI_NOR_HAS_LOCK,
>> +        .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | 
>> SPI_NOR_QUAD_READ,
>> +        .fixup_flags = SPI_NOR_4B_OPCODES,
>> +    }, {
>> +        .id = SNOR_ID(0xc8, 0x47, 0x1a),
>> +        .name = "gd25b512m",
>> +        .size = SZ_64M,
>> +        .flags = SPI_NOR_HAS_LOCK,
>> +        .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | 
>> SPI_NOR_QUAD_READ,
>> +        .fixup_flags = SPI_NOR_4B_OPCODES,
>> +    }, {
>> +        .id = SNOR_ID(0xc8, 0x47, 0x1b),
>> +        .name = "gd55b01ge",
>> +        .size = SZ_128M,
>> +        .flags = SPI_NOR_HAS_LOCK,
>> +        .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | 
>> SPI_NOR_QUAD_READ,
>> +        .fixup_flags = SPI_NOR_4B_OPCODES,
>> +    }, {
>> +        .id = SNOR_ID(0xc8, 0x67, 0x1b),
>> +        .name = "gd55lb01ge",
>> +        .size = SZ_128M,
>> +        .flags = SPI_NOR_HAS_LOCK,
>> +        .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | 
>> SPI_NOR_QUAD_READ,
>> +        .fixup_flags = SPI_NOR_4B_OPCODES,
>>       },
>>   };
>
>
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Hi Christophe,
It definitely miss the .size field for gd25q256, I will send one 
separated patch for this.

Best Regards,